ql7180 quickdsp tm data sheet rev b 1 ? ? ql7180 dsp data sheet combining embedded dsp blocks, performance, density and embedded ram 1.0 device highlights clock network 9 global clock networks 1 dedicated, 8 programmable 16 i/o (high drive) networks: 2 banks per i/o 20 quad-net networks: 5 per quadrant programmable i/o high performance enhanced i/o: less than 3 ns tco programmable slew rate control programmable i/o standards lvttl, lvcmos, pci, gtl+, sstl2, and sstl3 8 independent i/o banks 3 register configuration: input, output, oe parameterized ip free parameterized ip administered with a dsp wizard supports multiple and hierarchical ip instantiations applications signal processing operators signal processing functions networking / communications for voip speech / voice processing channel coding high speed customizable logic 0.25u, 5 layer metal cmos process 2.5 v vcc, 2.5 / 3.3 v drive capable i/o 512 programmable i/o 4,032 logic cells 660,000 max system gates muxed based architecture, non-volatile technology completely customizable for any digital applications dual port sram 36 blocks of dual-port sram 2,304 bit dual port high performance sram blocks total of 82,900 bits ram / rom / fifo wizard for automatic configuration configurable and cascadable array sizes of 2, 4, 9, and 18 < 3 ns access times, 300+ mhz fifo figure 1: embedded quickdsp block diagram
2 www.quicklogic.com ? 2001 quicklogic corporation ql7180 dsp data sheet 2.0 ac characteristics at vc c = 2.5v, ta=25 c (k=1.00) the ac specifications, logic cell diagrams and waveforms are provided below. figure 2: quickdsp logic cell table 1: logic cells symbol parameter propagation delay (ns) logic cells 1 tpd combinatorial delay: time taken by the combinatorial circuit to output 0.257 tsu setup time: the amount of time the synchronous input of the flip flop must be stable before the active clock edge 0.22 thl hold time: the amount of time the synchronous i nput of the flip flop must be stable after the active block edge 0 tclk clock to out delay: the amount of time the synch ronous input of the flip flop must be stable after the active block edge 0.255 tcwhi clock high time: the length of time that the clock stays high 0.46 tcwlo clock low time: the length of time that the clock stays low 0.46 tset set delay: amount of time between when the flip flop is ?set? (high) and when q is consequent ?set? (high) 0.18 treset reset delay: amount of time between when the flip flop is ?reset? (low) and when q is consequent ?reset? (low) 0.09 tsw set width: length of time that the set signal remains high (low if active low) 0.3 trw reset width: length of time that the reset signal remains high (low if active low) 0.3
ql7180 quickdsp tm data sheet rev b 3 ql7180 dsp data sheet figure 3: logic cell flip flop figure 4: logic cell flip flop timings - first waveform figure 5: logic cell flip fl op timings - second waveform
4 www.quicklogic.com ? 2001 quicklogic corporation ql7180 dsp data sheet figure 6: quickdsp global clock structure figure 7: global clock structure schematic table 2: quickdsp clock performance clock performance global dedicated macro 1.51 ns 1.59 ns i/o 2.06 ns 1.73 ns skew 0.55 ns 0.14 ns table 3: quickdsp input register cell symbol parameter propagation delay (ns) input register cell only tgckp global clock pin delay gckb global clock buffer delay
ql7180 quickdsp tm data sheet rev b 5 ql7180 dsp data sheet figure 8: quickram module table 4: ram cell synchronous write timing symbol parameter propagation delay (ns) ram cell synchronous write timing 1 tswa wa setup time to wclk: the amount of time the write address must be stable before the active edge of the write clock 0.675 thwa wa hold time to wclk: the amount of time the write address must be stable after the active edge of the write clock 0 tswd wd setup time to wclk: the amount of time the write data must be stable before the active edge of the write clock 0.654 thwd wd hold time to wclk: the amount of time the write data must be stable after the active edge of the write clock 0 tswe we setup time to wclk: the amount of time the write enable must be stable before the active edge of the write clock 0.623 thwe we hold time to wclk: the amount of time the write enable must be stable after the active edge of the write clock 0 twcrd wclk to rd (wa=ra) [5]: the amount of time between the active write clock edge and the time when the data is available at rd 4.38
6 www.quicklogic.com ? 2001 quicklogic corporation ql7180 dsp data sheet figure 9: ram cell synchronous write timing table 5: ram cell synchronous & asynchronous read timing symbol parameter propagation delay (ns) ram cell synchronous read timing 1 tsra ra setup time to rclk: the amount of time the read address must be stable before the active edge of the read clock 0.686 thra ra hold time to rclk: the amount of time the read address must be stable after the active edge of the read clock 0 tsre re setup time to rclk: the amount of time the read enable must be stable before the active edge of the read clock 0.243 thre re hold time to rclk: the amount of time the read enable must be stable after the active edge of the read clock 0 trcrd rclk to rd [5]: the amount of time between the active read clock edge and the time when the data is available at rd 4.38 ram cell synchronous read timing rpdrd ra to rd [5]: amount of time between when the read address is input and when the data is output 2.06
ql7180 quickdsp tm data sheet rev b 7 ql7180 dsp data sheet figure 10: ram cell synchronou s & asynchronous read timing figure 11: quickdsp cell i/o
8 www.quicklogic.com ? 2001 quicklogic corporation ql7180 dsp data sheet figure 12: quickdsp input register cell table 6: input register cell symbol parameter propagation delay (ns) input register cell only 1 tisu input register setup time: the amount of time the synchronous input of the flip flop must be stable before the active clock edge 3.12 tih input register hold time: the amount of time the synchronous input of the flip flop must be stable after the active clock edge 0 ticlk input register clock to q: the amount of time taken by the flip flop to output after the active clock edge 1.08 tirst input register reset delay: amount of time between when the flip flop is ?reset?(low) and when q is consequently ?reset? (low) 0.99 tiesu input register clock enable setup time: the amount of time ?enable? must be stable before the active clock edge 0.37 tieh input register clock enable time: the amount of time ?enable? must be stable after the active clock edge 0
ql7180 quickdsp tm data sheet rev b 9 ql7180 dsp data sheet figure 13: quickdsp in put register cell timing table 7: standard input delays symbol parameter propagation delay (ns) standard input delays to get the total input delay and this delay to tisu 1 tsid (lvttl) lvttl input delay: low voltage ttl for 3.3v applications 0.34 tsid (lvcmos2) lvcmos2 input delay: low voltage cmos for 2.5v and lower applications 0.42 tsid (gtl+) gtl+ input delay : gunning transceiver logic 0.68 tsid (sstl3) sstl3 input delay: stub series terminated logic for 3.3v 0.55 tsid (sstl2) sstl2 input delay: stub series terminated logic for 2.5v 0.607
10 www.quicklogic.com ? 2001 quicklogic corporation ql7180 dsp data sheet figure 14: quickdsp output register cell table 8: quickdsp output register cell symbol parameter propagation delay (ns) output register cell only 1 toutlh output delay low to high (10% of h) 0.40 touthl output delay high to low (90% of h) 0.55 tpzh output delay tri-state to high (10% of z) tpzl output delay tri-state to low (90% of z) tphz output delay high to tri-state 3.07 tplz output delay low to tri-state 2.53
ql7180 quickdsp tm data sheet rev b 11 ql7180 dsp data sheet figure 15: quickdsp outp ut register cell timing table 9: vccio = 3.3 v fast slew slow slew rising edge 2.8 v/ns 1.0 v/ns falling edge 2.86 v/ns 1.0 v/ns table 10: vccio = 2.5 v fast slew slow slew rising edge 1.7 v/ns 0.6 v/ns falling edge 1.9 v/ns 0.6 v/ns
12 www.quicklogic.com ? 2001 quicklogic corporation ql7180 dsp data sheet 3.0 dc characteristics the dc specifications are provided in the tables below. table 11: absolute maximum ratings v cc voltage -0.5 to 3.6v dc input current 20 ma v ccio voltag e -0.5 to 4.6v esd pad protection 2000v v ref voltage 2.7v storage temperature -65c to +150c input voltage -0.5v to v ccio +0.5v maximum lead temperature 300c latch-up immunity 100 ma table 12: operating range symbol parameter military industrial commercial unit min max min max min max vcc supply voltage 2.3 2.7 2.3 2.7 2.3 2.7 v vccio i/o input tolerance voltage 2.3 3.6 2.3 3.6 2.3 3.6 v ta ambient temperature -55 -40 85 0 70 c tc case temperature 125 c k delay factor -4 speed grade 0.42 2.3 0.43 2.16 0.47 2.11 n/a -5 speed grade 0.42 1.92 0.43 1.80 0.46 1.76 n/a -6 speed grade 0.42 1.35 0.43 1.26 0.46 1.23 n/a -7 speed grade 0.42 1.22 0.43 1.14 0.46 1.11 n/a table 13: dc input and output levels v ref v il v ih v ol v oh i ol i oh v min v max v min v max v min v max v max v min ma ma lv t t l n/a n/a -0.3 0.8 2.0 v ccio -0.3 0.4 24. 2.0 -2.0 lv c m o s 2 n/a n/a -0.3 0.7 1.7 v ccio -0.3 0.7 1.7 2.0 -2.0 gtl+ 0.88 1.12 -0.3 v ref -2.0 v ref +2.0 v ccio -0.3 0.6 n/a 40 n/a pci n/a n/a -0.3 0.3xv cc 0.5xv cc v ccio -0.5 0.1xv cc 0.9xv c 1.5 -0.5 sstl2 1.15 1.35 -0.3 v ref -0.18 v ref +0.18 v ccio +0.3 0.74 1.76 7.6 -7.6 sstl3 1.3 1.7 -0.3 v ref -0.2 v ref +2.0 v ccio +0.3 1.10 1.90 9 -8
ql7180 quickdsp tm data sheet rev b 13 ql7180 dsp data sheet 4.0 pin descriptions table 14: pin descriptions pin function description tdi/rsi test data in for jtag /ram init. serial data in hold high during normal operation. connects to serial prom data in for ram initialization. connect to vcc if unused trstb/rro active low reset for jtag /ram init. reset out hold low during normal operation. connects to serial prom reset for ram initialization. connect to gnd if unused tms test mode select for jtag hold high during normal operation. connect to vcc if not used for jtag tck test clock for jtag hold high or low during normal operation. connect to vcc or ground if not used for jtag tdo/rco test data out for jtag /ram init. clock out connect to serial prom clock for ram initialization. must be left unconnected if not used for jtag or ram initialization i/gclk high-drive input and/or global network driver can be configured as either or both i/o input/output pin can be configured as an input and/or output vcc power supply pin connect to 2.5v supply vccio input voltage tolerance pin connect to 3.3 volt supply if 3.3 volt input tolerance is required, otherwise connect to 2.5v supply gnd ground pin connect to ground pllin pll clock input clock input for pll dedclk dedicated clock pin low skew global clock gndpll ground pin for pll connect to gnd inref differential reference voltage connect to reference voltage or ground if used for non-differential input pllout pll output pin dedicated pll output pin. otherwise may be left unconnected ioctrl highdrive input can be used as highdrive input or cloc k to i/o register within the same bank. tied low or high if unused
14 www.quicklogic.com ? 2001 quicklogic corporation ql7180 dsp data sheet 4.1 recommended unused pin term inations for the quickdsp devices all unused, general purpose i/o pins can be tied to vcc, gnd or hiz (high impe dance) internally using the configuration editor. the option is given in th e right-bottom corner of the configuration window. the use the configuration editor go to: tools/configuration pins. the rest of the pins should be terminated at the board level in the following manner: note: x -> number, y -> alphabetical character figure 16: ordering information table 15: recommended unused pin terminations signal name recommended termination pllout unused pll output pins must be connected to eit her vcc or gnd so that their associated input buffer never floats. utilized pll output pins that route the pll clock outside of the chip, do not need to be tied to either vcc or gnd. ioctrl any unused pins of this type must be connected to either vcc or gnd. clk/pllin any unused clock pins sh ould be connected to vcc or gnd. pllrst if a pll module is not used, then the associat ed pllrst must be connected to vcc, under normal operation use it as needed. inref if an i/o bank does not requi re the use of inref signal the pin should be connected to gnd. ql 7180 - 4 ps672 c quicklogic device quickdsp device part number speed grade 4 = quick 5 = fast 6 = faster 7 = fastest operating range c = commercial i = industrial m = military package code pt280 = 280-pin fpbga ps484 = 484-pin bga (1.0mm) ps672 = 672-pin bga (1.0mm) pb516 = 516-pin bga (1.27mm)
ql7180 quickdsp tm data sheet rev b 15 ql7180 dsp data sheet 5.0 280 pbga pinout diagram top bottom quickdsp ql7180-4pt280c pin a1 corner
16 www.quicklogic.com ? 2001 quicklogic corporation ql7180 dsp data sheet 6.0 280 pbga pinout table table 16: 280 pbga pinout table 280 pbga function 280 pbga function 280 pbga function 280 pbga function 280 pbga function 280 pbga function a1 pllout<3> c10 clk<5>/plli n<3> e19 ioctrl k16 i/o r4 i/o u13 i/o a2 gndpll<0> c11 vccio f1 inref k17 i/o r5 gnd u14 ioctrl a3 i/o c12 i/o f2 ioctrl k18 i/o r6 gnd u15 vccio a4 i/o c13 i/o f3 i/o k19 trstb r7 vcc u16 i/o a5 i/o c14 i/o f4 i/o l1 i/o r8 vcc u17 tdo a6 ioctrl c15 vccio f5 gnd l2 i/o r9 gnd u18 pllrst<2> a7 i/o c16 i/o f15 vcc l3 vccio r10 gnd u19 i/o a8 i/o c17 i/o f16 ioctrl l4 i/o r11 vcc v1 pllout<2> a9 i/o c18 i/o f17 i/o l5 vcc r12 vcc v2 gndpll<3> a10 clk<7> c19 i/o f18 i/o l15 gnd r13 vcc v3 gnd a11 i/o d1 i/o f19 i/o l16 i/o r14 vcc v4 i/o a12 i/o d2 i/o g1 i/o l17 vccio r15 gnd v5 i/o a13 i/o d3 i/o g2 i/o l18 i/o r16 i/o v6 ioctrl a14 ioctrl d4 i/o g3 ioctrl l19 i/o r17 vccio v7 i/o a15 i/o d5 i/o g4 i/o m1 i/o r18 i/o v8 i/o a16 i/o d6 i/o g5 vcc m2 i/o r19 i/o v9 i/o a17 i/o d7 i/o g15 vcc m3 i/o t1 i/o v10 clk<1> a18 pllrst<1> d8 i/o g16 i/o m4 i/o t2 i/o v11 clk<4>dedc lk/pllin<0> a19 gnd d9 clk<8> g17 i/o m 5 vcc t3 i/o v12 i/o b1 pllrst<0> d10 i/o g18 i/o m15 vcc t4 i/o v13 i/o b2 gnd d11 i/o g19 i/o m16 inref t5 i/o v14 inref b3 i/o d12 i/o h1 i/o m17 i/o t6 ioctrl v15 i/o b4 i/o d13 inref h2 i/o m18 i/o t7 i/o v16 i/o b5 i/o d14 i/o h3 i/o m19 i/o t8 i/o v17 i/o b6 inref d15 i/o h4 i/o n1 ioctrl t9 i/o v18 gndpll<2> b7 i/o d16 i/o h5 vcc n2 i/o t10 i/o v19 gnd b8 i/o d17 i/o h15 vcc n3 i/o t11 clk<3>/plli n<1> w1 gnd b9 tms d18 i/o h16 vcc n4 i/o t12 i/o w2 pllrst<3> b10 clk<6> d19 i/o h17 i/o n5 vcc t13 i/o w3 i/o b11 i/o e1 i/o h18 i/o n15 vcc t14 i/o w4 i/o b12 i/o e2 i/o h19 i/o n16 i/o t15 i/o w5 i/o b13 ioctrl e3 vccio j1 i/o n17 i/o t16 i/o w6 i/o b14 i/o e4 i/o j2 i/o n18 ioctrl t17 vccpll<2> w7 i/o b15 i/o e5 gnd j3 vccio n19 ioctrl t18 i/o w8 i/o b16 i/o e6 vcc j4 i/o p1 i/o t19 i/o w9 tdi b17 vccpll<1> e7 vcc j5 gnd p2 i/o u1 i/o w10 clk<2>/plli n<2> b18 gndpll<1> e8 vcc j15 vcc p3 ioctrl u2 i/o w11 i/o b19 pllout<0> e9 vcc j16 i/o p4 inref u3 vccpll<3> w12 i/o c1 i/o e10 gnd j17 vccio p5 vcc u4 i/o w13 i/o c2 vccpll<0> e11 gnd j18 i/o p15 gnd u5 vccio w14 ioctrl c3 i/o e12 vcc j19 i/o p16 i/o u6 inref w15 i/o c4 i/o e13 vcc k1 vcc p17 i/o u7 i/o w16 i/o c5 vccio e14 gnd k2 tck p18 i/o u8 i/o w17 i/o c6 ioctrl e15 gnd k3 i/o p19 i/o u9 vccio w18 i/o c7 i/o e16 i/o k4 i/o r1 i/o u10 clk<0> w19 pllout<1> c8 i/o e17 vccio k5 gnd r2 i/o u11 vccio c9 vccio e18 inref k15 gnd r3 vccio u12 i/o ql7180 quickdsp tm data sheet rev b 17 ql7180 dsp data sheet 7.0 484 pbga pinout diagram top bottom quickdsp ql7180-4ps484c 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c e d f g h k j l m n r p t u v y w 22 21 a b aa pin a1 corner pin a1
18 www.quicklogic.com ? 2001 quicklogic corporation ql7180 dsp data sheet 8.0 484 pbga pinout table table 17: 484 pbga pinout table 484 pbga function 484 pbga function 484 pbga function 484 pbga function 484 pbga function 484 pbga function a1 i/o c18 i/o f13 i/o j8 vcc m3 i/o p20 i/o a2 pllrst<3> c19 i/o f14 vccio j9 gnd m4 clk<3>/pllin<1> p21 i/o a3 i/o c20 gndpll<0> f15 i/o j10 vcc m5 i/o p22 i/o a4 i/o c21 i/o f16 vccio j11 vcc m6 vccio r1 i/o a5 i/o c22 i/o f17 i/o j12 gnd m7 clk<1> r2 inref a6 i/o d1 i/o f18 i/o j13 vcc m8 vcc r3 i/o a7 i/o d2 i/o f19 i/o j14 gnd m9 vcc r4 i/o a8 ioctrl d3 i/o f20 ioctrl j15 vcc m10 gnd r5 i/o a9 i/o d4 i/o f21 i/o j16 i/o m11 gnd r6 i/o a10 i/o d5 i/o f22 ioctrl j17 vccio
